A solid image pick-up element using CCD used for an area sensor or the like includes a photoelectric converting portion of a photodiode or the like, and a charge transmitting portion having a charge transmitting electrode for transmitting a signal charge from the photoelectric converting portion. A plurality of pieces of charge transmitting electrodes are arranged contiguously on a charge transmitting path formed at a semiconductor substrate and are successively driven.
In recent years, in a solid image pick-up element, a request for high resolution formation and high sensitivity formation is more and more increasing and an increase in a number of image pick-up pixels is progressed to more than giga pixels. Under such a situation, in order to achieve high resolution without making a chip size large-sized, it is necessary to achieve highly integrated formation by reducing an area per unit pixel.
On the other hand, when an area of a photodiode constituting a photoelectric converting portion is reduced, a sensitivity is deteriorated and therefore, an area of a photodiode region needs to be ensured. Hence, various researches have been carried out in order to achieve miniaturization of a chip while ensuring an area occupied by the photodiode region by achieving miniaturization of wirings of a charge transmitting portion and a peripheral circuit and reducing a rate of areas of the wirings.
Under such a situation, it becomes an important technical problem to maintain flatness of an interlayer insulating film between wiring layers in order to realize highly integrated formation by miniaturization of the wirings. Furthermore, a substrate (silicon substrate) fabricated with a solid image pick-up element is mounted by being laminated with a filter and a lens. Therefore, positional accuracies of the lens and the photoelectric converting portion become important and a distance thereof, that is, a distance in a height direction becomes a significant problem in view of positional accuracy in producing steps and a sensitivity (photoelectric conversion efficiency) when used.
Hence, in order to promote flatness, there is proposed a structure in which the charge transmitting portion is constructed by a structure of a single layer electrode. In CCD, a gap between electrodes becomes an important factor for determining a transmitting efficiency and it is important how to reduce the gap between electrodes. However, in forming an electrode pattern by a normal photolithography technology, 1 μm constitutes a limit and it is difficult to form the gap smaller than 1 μm. Further, in miniaturization of a distance between electrodes, also an aspect ratio is obliged to be enlarged and also a technology of embedding an insulating film to the gap between electrodes which is very small and is provided with the large aspect ratio is also extremely difficult.
Therefore, miniaturization of the gap between electrodes is extremely serious and promotion of pattern accuracy becomes a serious problem. Further, also miniaturization of a peripheral circuit portion is similarly requested. Under such a situation, a flatness of a surface of a substrate becomes an extremely important problem in promoting the pattern accuracy in the photolithography step and filling the insulting film into the gap between electrodes. Although in a background art, various trials have been carried out in pursuit for the flatness of the surface, the request for promoting the pattern accuracy accompanied by miniaturization is more and more increasing all the more.
Further, according to a solid image pick-up element using a charge transmitting electrode having a single layer structure of a background art, in miniaturization of a gap between electrodes, in order to achieve miniaturization exceeding a resolution of photolithography, there is also proposed a method of achieving flatness by resist etch back or CMP (chemical mechanical polishing) method after forming a pattern of a first layer conductive film and thereafter forming an insulting film between electrodes and laminating a second layer conductive film at an upper layer thereof.
For example, single layer formation of an electrode is carried out by using a polycrystal silicon or an amorphous silicon film as a charge transmitting electrode, forming a first layer wiring, thereafter, oxidizing a surface of a pattern of the first layer wiring, piling up a polycrystal silicon or an amorphous silicon film constituting a second layer of a transmitting electrode, coating a resist and etching an entire face thereof by a resist etch back method.
An example thereof will be explained in reference to FIG. 10 through FIG. 12. First, a surface of an n-type silicon substrate 1 is formed with a field oxide film having a film thickness of about 600 nm at a region surrounding an image pick-up region by LOCOS method to isolate elements and thereafter an element region is formed. That is, a silicon oxide film 2a having a film thickness of 15 through 35 nm, a silicon nitride film 2b having a film thickness of 50 nm and a silicon oxide film 2c having a film thickness of 10 nm are formed to form a gate oxide film 2 having a three layers structure. At this occasion, a surface of the substrate before forming the element region is brought into a state of projecting a field oxide film 10.
Successively, a first layer doped amorphous silicon film 3a having a film thickness of 250 nm is formed on the gate oxide film 2 and a silicon oxide film 4a and a silicon nitride film 4b are formed (FIG. 10A).
Successively, a resist is coated at an upper layer thereof.
Further, as shown by FIG. 10B, exposure, development and rinsing are carried out by using a desired mask by photolithography to form a resist pattern R1 having a pattern width of 0.3 through several μm.
Thereafter, as shown by FIG. 10C, by constituting a mask by the resist pattern R1, the silicon oxide film 4a and the silicon nitride film 4b are etched to form a mask pattern for patterning a first electrode.
Further, the resist pattern is exfoliated to remove by ashing (FIG. 11D), by constituting a mask by the mask pattern, constituting an etching stopper by the silicon nitride film 2b of the gate oxide film 2, the first layer doped amorphous silicon film 3a is etched to remove to form the first electrode (FIG. 11E).
Successively, an insulating film between electrodes 5 is formed at a surface of the pattern of the first electrode by thermal oxidation (FIG. 11F), further, a silicon oxide film (HTO oxide film) 6 is formed at an upper layer thereof (FIG. 12G).
Further, a second layer doped amorphous silicon film 3b is formed at an upper layer thereof (FIG. 12H).
Thereafter, the second layer doped amorphous silicon film 3b is flattened by CMP (FIG. 12I).
In this way, a second electrode comprising the second layer doped amorphous silicon film 3b is formed to form a solid image pick-up element electrode having a flat surface.
In the case of the method, when the second electrode is formed by separating the second layer doped amorphous silicon film by removing the second layer doped amorphous silicon film on the first electrode by flattening to remove the second layer doped amorphous silicon film by CMP, the field oxide film 10 is higher than the surface of the first electrode and cannot be machined by CMP.
The same goes with resist etch back.
In this way, there is a case in which a height of a nonimage pick-up region formed with an amplifying circuit or the like becomes lower than that of an effective image pick-up region having a charge transmitting electrode. In such a case, there poses a problem that machining by CMP is difficult. Further, also in the case of flattening by resist etch back, separation of electrodes by flattening similarly becomes difficult.
Further, there is also proposed a constitution in which a height of a surface formed with a field oxide film is formed to be lower than a height of a surface of a charge transmitting electrode in order to enable to carry out machining by CMP (JP-A-11-26743).
However, even when separation of electrodes can be carried out, in the case in which the surface of the substrate is not sufficiently flat, the pattern accuracy of the first layer doped amorphous silicon film cannot sufficiently be achieved. The more miniaturized the pattern, the more the problem is brought into a serious state, and in miniaturization, the problem is revealed.
However, even when the filed oxide film is lower than the electrode, in the case of forming a wiring on a field oxide film, a stepped difference is brought about to pose a problem of bringing about a nonuniformity in a sensitivity or color at a peripheral portion of an image pick-up screen.
Furthermore, when a region having a small density of the first layer doped amorphous silicon film is disposed at a peripheral edge portion of a wafer, in the case of forming a resist by spin coating, a surface level of the resist becomes low, as a result, there is a case of bringing about a reduction in the second doped amorphous silicon film at the peripheral edge portion of the wafer.
Further, at the region having the small density of the first doped amorphous silicon film not only at the peripheral edge portion of the wafer but also a region other than a wiring region and a photodiode portion on a semiconductor substrate, there is a case of forming a region having a thin resist pattern. In such a case, a problem of bringing about a dispersion in a wiring resistance is posed.
In such a case, there poses a problem of bringing about a dispersion in a wiring resistance at a periphery. Further, there also is a case of deteriorating a transmitting efficiency by a dispersion in a film thickness of a charge transmitting electrode at a peripheral portion. Further, the dispersion increases a nonuniformity in film thicknesses and dispersion in shapes of various films of a flattened film, a microlens, a color filter and the like of layers upward from the charge transmitting electrode to also pose a problem of bringing about shading, a dispersion in sensitivity and a deterioration of smear by stray light.
Therefore, there poses a problem that it is difficult to deal with miniaturization or a further increase in a sensitivity by the above-described methods.
In this way, according to the solid image pick-up element of the background art, in accordance with miniaturization, flatness of the surface of the semiconductor substrate becomes a serious problem and a higher degree of flatness to a degree which is not conceivable by a size of the background art has been requested.